1. Technical Field
The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly, to a wafer stacked package (WSP) having a vertical heat emission path inside a WSP semiconductor chip, and a method of fabricating the same.
2. Description of the Related Art
Conventionally, the usual method of fabricating a semiconductor memory device with high integration density is to apply the design rules of fabricating a thinner wafer and positioning many integrated circuits within the small area of the wafer, so that elements such as transistors and capacitors are three-dimensionally arranged. As an alternative, semiconductor devices are being developed to improve their integration density, by vertically stacking thinner semiconductor chips, so that many semiconductor chips are stacked within a single semiconductor package. The stacked semiconductor chip method for improving the integration density of a semiconductor memory device, using the semiconductor package fabricating technology, has many merits in the cost and time required for research and development and in realizing necessary processes, compared with the conventional method for improving the integrity density during the wafer fabrication process. Accordingly, significant research is directed towards the semiconductor package fabricating technology to improve the integration density of a semiconductor memory device.
In a semiconductor chip of a semiconductor memory device, such as a NAND flash memory device, many input/output pads (IiO pads) are placed in one area of the semiconductor chip. This can cause a ‘hot spot’ phenomenon when the NAND flash device operates at high speed. When a stack is formed of four or more chips with a relatively high power consumption, such as high-speed DDR DRAMs, a large amount of heat is generated. In a WSP particularly, the heat in the middle of the stack can not be effectively dissipated, since a significant amount of
an adhesive is used for bonding the stack. The adhesive blocks the heat conduction between the stacked chips. This reduces the reliability of the WSP.
A system in package (SIP) has been the subject of significant research, as well. The SIP is a single integrated semiconductor package, manufactured by stacking a microprocessor or microcontroller semiconductor chip and a memory device semiconductor chip. However, for the SIP to be practical, a way must be found to effectively dissipate the great amount of heat generated by the microprocessor or microcontroller.
FIG. 1 is a sectional view for explaining a conventional WSP 50, and FIG. 2 is an enlargement of Part II of FIG. 1.
As illustrated in FIGS. 1 and 2, in the conventional WSP 50, four semiconductor chips 16 are stacked on a substrate 10 on which a printed circuit pattern is formed, and each semiconductor chip 16 is electrically connected to the substrate 10 under the semiconductor chips 16, by a via contact 18. In FIG. 1, reference numeral 20 indicates sealing resin for sealing the upper part of the substrate 10 and the semiconductor chips 16.
Electrical connection of the upper and lower semiconductor chips 16 is made by the via contact 18 composed of metal materials, as shown in FIG. 2. Regions of the semiconductor chips 16 other than those electrically connected by the via contacts 18 are physically connected by an adhesive 22.
FIG. 3 is a graph of simulated connection temperature vs. heat generated in two semiconductor chips in a WSP having four stacked semiconductor chips.
In FIG. 3, the WSP was cooled by natural convection currents, and the two semiconductor chips were at the top of a stack of four DDR DRAMs. The X axis indicates the power consumption of the two semiconductor chips, and the Y axis indicates the temperature. When the power consumption is 0.2 W or more, the temperature of the WSP is expected to be more than 85° C., which is the maximum temperature to guarantee reliability of the product. Also, when NAND flash products or microprocessor and memory products are stacked, the surface temperature of the semiconductor package is expected to be much higher, due to the hotspot phenomenon and the great amount of heat generated by the microprocessor. Accordingly, a means for effectively dissipating the great amount of heat from the WSP is needed, to improve the reliability of the WSP.